very low power cmos sram 1m x 8 bit bs62lv8001 r0201-bs62lv8001 revision 2.4 oct. 2008 1 pb-free and green package materials are compliant to rohs ? features y wide v cc operation voltage : 2.4v ~ 5.5v y very low power consumption : v cc = 3.0v operation current : 31ma (max.) at 55ns 2ma (max.) at 1mhz standby current : 4/8ua (max.) at 70/85 o c v cc = 5.0v operation current : 76ma (max.) at 55ns 10ma (max.) at 1mhz standby current : 25/50ua (max.) at 70/85 o c y high speed access time : -55 55ns (max.) at v cc : 3.0~5.5v -70 70ns (max.) at v cc : 2.7~5.5v y automatic power down when chip is deselected y easy expansion with ce1, ce2 and oe options y three state outputs and ttl compatible y fully static operation y data retention supply voltage as low as 1.5v ? description the bs62lv8001 is a high performance, very low power cmos static random access memory organized as 1,048,576 by 8 bits and operates form a wide range of 2.4v to 5.5v supply voltage. advanced cmos technology and ci rcuit techniques provide both high speed and low power features with maximum cmos standby current of 8/50ua at vcc=3/5v at 85 o c and maximum access time of 55/70ns. easy memory expansion is provided by an active low chip enable (ce1), an active high chip enable (ce2), and active low output enable (oe) and three-state output drivers. the bs62lv8001 has an automatic power down feature, reducing the power consumption significant ly when chip is deselected. the bs62lv8001 is available in dice form, jedec standard 44-pin tsop ii and 48-ball bga package. ? power consumption power dissipation standby (i ccsb1 , max) operating (i cc , max) v cc =5.0v v cc =3.0v product family operating temperature v cc =5.0v v cc =3.0v 1mhz 10mhz f max. 1mhz 10mhz f max. pkg type bs62lv8001dc dice bs62lv8001ec tsop ii-44 bs62lv8001fc commercial +0 o c to +70 o c 25ua 4.0ua 9ma 39ma 75ma 1.5ma 19ma 30ma bga-48-0912 bs62lv8001ei tsop ii-44 bs62lv8001fi industrial -40 o c to +85 o c 50ua 8.0ua 10ma 40ma 76ma 2ma 20ma 31ma bga-48-0912 ? pin configurations ? block diagram brilliance semiconductor, inc. reserves the right to change products and specifications without notice. a4 a3 a2 a1 a0 ce1 nc nc dq0 dq1 vcc vss dq2 dq3 nc nc we a19 a18 a17 a16 a15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 bs62lv8001ec bs62lv8001ei 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 a5 a6 a7 oe ce2 a8 nc nc dq7 dq6 vss vcc dq5 dq4 nc nc a9 a10 a11 a12 a13 a14 g h f e d c b a 1 2 3 4 5 6 a9 a11 a10 a19 a12 a14 a13 a15 we nc nc nc dq7 a17 a16 a7 vss vcc dq2 dq1 dq6 dq5 nc a5 oe a3 a0 a6 a4 a1 a2 ce2 nc nc nc ce1 dq4 nc 48-ball bga top view nc nc dq0 vss vcc dq3 nc a18 nc a8 address input buffer row decoder memory array 2048 x 4096 column i/o write driver sense am p column decoder address input buffer a8 a2 a1 a0 a10 data input buffer control dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 a13 a17 a15 a18 a16 a14 a12 a7 a6 a5 a4 8 8 8 8 18 512 4096 2048 22 a9 a11 data output buffer a3 ce1 ce2 we oe v cc v ss a19
bs62 l v 8001 r0201-bs62lv8001 revision 2.4 oct. 2008 2 ? pin descriptions name function a0-a19 address input these 20 address inputs select one of the 1,048,576 x 8-bit in the ram ce1 chip enable 1 input ce2 chip enable 2 input ce1 is active low and ce2 is active high . both chip enables must be active when data read form or write to the device. if ei ther chip enable is not active, the device is deselected and is in standby power mode. th e dq pins will be in the high impedance state when the device is deselected. we write enable input the write enable input is active low and c ontrols read and write operations. with the chip selected, when we is high and oe is low, output data will be present on the dq pins; when we is low, the data present on the dq pins will be written into the selected memory location. oe output enable input the output enable input is active low. if the output enable is active while the chip is selected and the write enable is inactive, dat a will be present on the dq pins and they will be enabled. the dq pins will be in the high impendence state when oe is inactive. dq0-dq7 data input/output ports there 8 bi-directional ports are used to read data from or write data into the ram. v cc power supply v ss ground ? truth table mode ce1 ce2 we oe i/o operation v cc current h x x x not selected (power down) x l x x high z i ccsb , i ccsb1 output disabled l h h h high z i cc read l h h l d out i cc write l h l x d in i cc ? absolute maximum ratings (1) symbol parameter rating units v term terminal voltage with respect to gnd -0.5 (2) to 7.0 v t bias temperature under bias -40 to +125 o c t stg storage temperature -60 to +150 o c p t power dissipation 1.0 w i out dc output current 20 ma 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational secti ons of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. ?2.0v in case of ac pulse width less than 30 ns. ? operating range rang ambient temperature v cc commercial 0 o c to + 70 o c 2.4v ~ 5.5v industrial -40 o c to + 85 o c 2.4v ~ 5.5v ? capacitance (1) (t a = 25 o c, f = 1.0mhz) symbol pamameter conditions max. units c in input capacitance v in = 0v 6 pf c io input/output capacitance v i/o = 0v 8 pf 1. this parameter is guaranteed and not 100% tested.
bs62 l v 8001 r0201-bs62lv8001 revision 2.4 oct. 2008 3 ? dc electrical characteristics (t a =-40 o c to +85 o c) parameter name parameter test conditions min. typ. (1) max. units v cc power supply 2.4 -- 5.5 v v il input low voltage -0.5 (2) -- 0.8 v v ih input high voltage 2.2 -- v cc +0.3 (3) v i il input leakage current v in = 0v to v cc -- -- 1 ua i lo output leakage current v i/o = 0v to v cc , ce1= v ih or ce2= v il , or oe = v ih -- -- 1 ua v ol output low voltage v cc = max, i ol = 2.0ma -- -- 0.4 v v oh output high voltage v cc = min, i oh = -1.0ma 2.4 -- -- v v cc =3.0v 31 i cc (5) operating power supply current ce1 = v il and ce2 = v ih , i dq = 0ma, f = f max (4) v cc =5.0v -- -- 76 ma v cc =3.0v 2 i cc1 operating power supply current ce1 = v il and ce2 = v ih , i dq = 0ma, f = 1mhz v cc =5.0v -- -- 10 ma v cc =3.0v 1.0 i ccsb standby current ? ttl ce1 = v ih , or ce2 = v il , i dq = 0ma v cc =5.0v -- -- 2.0 ma v cc =3.0v 0.8 8.0 i ccsb1 (6) standby current ? cmos ce1 R v cc -0.2v or ce2 Q 0.2v, v in R v cc -0.2v or v in Q 0.2v v cc =5.0v -- 3.5 50 ua 1. typical characteristics are at t a =25 o c and not 100% tested. 2. undershoot: -1.0v in case of pulse width less than 20 ns. 3. overshoot: v cc +1.0v in case of pulse width less than 20 ns. 4. f max =1/t rc. 5. i cc (max.) is 30ma/75ma at v cc =3.0v/5.0v and t a =70 o c. 6. i ccsb1(max.) is 4.0ua/25ua at v cc =3.0v/5.0v and t a =70 o c. ? data retention characteristics (t a = -40 o c to +85 o c) symbol parameter test conditions min. typ. (1) max. units v dr v cc for data retention ce1 R v cc -0.2v or ce2 Q 0.2v, v in R v cc -0.2v or v in Q 0.2v 1.5 -- -- v i ccdr (3) data retention current ce1 R v cc -0.2v or ce2 Q 0.2v, v in R v cc -0.2v or v in Q 0.2v -- 0.4 4.0 ua t cdr chip deselect to data retention time 0 -- -- ns t r operation recovery time see retention waveform t rc (2) -- -- ns 1. v cc =1.5v, t a =25 o c and not 100% tested. 2. t rc = read cycle time. 3. i ccrd(max.) is 2.0ua at t a =70 o c. ? low v cc data retention waveform (1) (ce1 controlled) data retention mode v cc t cdr v cc t r v ih v ih ce1 R v cc - 0.2v v dr R 1.5v ce1 v cc
bs62 l v 8001 r0201-bs62lv8001 revision 2.4 oct. 2008 4 ? low v cc data retention waveform (2) (ce2 controlled) ? ac test conditions (test load and input/output reference) input pulse levels vcc / 0v input rise and fall times 1v/ns input and output timing reference level 0.5vcc t clz , t olz , t chz , t ohz , t whz c l = 5pf+1ttl output load others c l = 30pf+1ttl 1. including jig and scope capacitance. ? key to switching waveforms waveform inputs outputs must be steady must be steady may change from ?h? to ?l? will be change from ?h? to ?l? may change from ?l? to ?h? will be change from ?l? to ?h? don?t care any change permitted change : state unknow does not apply center line is high inpedance ?off? state ? ac electrical characteristics (t a = -40 o c to +85 o c) read cycle jedec parameter name paraneter name description cycle time : 55ns (v cc = 3.0~5.5v) min. typ. max. cycle time : 70ns (v cc = 2.7~5.5v) min. typ. max. units t avax t rc read cycle time 55 -- -- 70 -- -- ns t av q x t aa address access time -- -- 55 -- -- 70 ns t e1lqv t acs1 chip select access time (ce1) -- -- 55 -- -- 70 ns t e2hqv t acs2 chip select access time (ce2) -- -- 55 -- -- 70 ns t glqv t oe output enable to output valid -- -- 25 -- -- 30 ns t e1lqx t clz1 chip select to output low z (ce1) 10 -- -- 10 -- -- ns t e2hqx t clz2 chip select to output low z (ce2) 10 -- -- 10 -- -- ns t glqx t olz output enable to output low z 10 -- -- 10 -- -- ns t e1hqz t chz1 chip select to output high z (ce1) -- -- 30 -- -- 35 ns t e2lqz t chz2 chip select to output high z (ce2) -- -- 30 -- -- 35 ns t ghqz t ohz output enable to output high z -- -- 25 -- -- 30 ns t av q x t oh data hold from address change 10 -- -- 10 -- -- ns ce2 data retention mode v cc t cdr v cc t r v il v il v cc v dr R 1.5v ce2 Q 0.2v c l (1) 1 ttl output all input pulses 90% v cc gnd rise time : 1v/ns fall time : 1v/ns 90%
bs62 l v 8001 r0201-bs62lv8001 revision 2.4 oct. 2008 5 ? switching waveforms (read cycle) read cycle 1 (1,2,4) read cycle 2 (1,3,4) read cycle 3 (1, 4) notes: 1. we is high in read cycle. 2. device is continuously selected when ce1 = v il and ce2= v ih . 3. address valid prior to or coincident with ce1 transition low and/or ce2 transition high. 4. oe = v il . 5. transition is measured 500mv from steady state with c l = 5pf. the parameter is guaranteed but not 100% tested. t rc t oh t aa d out address t oh t clz (5) d out ce2 ce1 t a cs2 t a cs1 t chz1 , t chz2 (5) t oh t rc t oe t clz2 (5) t chz2 (1 , 5) d out ce2 ce1 oe address t clz1 (5) t a cs1 t acs2 t chz1 (1 , 5) t ohz (5) t olz t aa
bs62 l v 8001 r0201-bs62lv8001 revision 2.4 oct. 2008 6 ? ac electrical characteristics (t a = -40 o c to +85 o c) write cycle jedec parameter name paraneter name description cycle time : 55ns (v cc = 3.0~5.5v) min. typ. max. cycle time : 70ns (v cc = 2.7~5.5v) min. typ. max. units t avax t wc write cycle time 55 -- -- 70 -- -- ns t av w l t as chip select to end of write 0 -- -- 0 -- -- ns t av w h t aw address set up time 40 -- -- 50 -- -- ns t e1lwh t cw address valid to end of write 40 -- -- 50 -- -- ns t wlwh t wp write pulse width 30 -- -- 35 -- -- ns t whax t wr1 write recovery time (ce1, we) 0 -- -- 0 -- -- ns t e2lax t wr2 write recovery time (ce2) 0 -- -- 0 -- -- ns t wlqz t whz write to output high z -- -- 25 -- -- 30 ns t dvwh t dw data to write time overlap 25 -- -- 30 -- -- ns t whdx t dh data hold from write time 0 -- -- 0 -- -- ns t ghqz t ohz output disable to output in high z -- -- 25 -- -- 30 ns t whqx t ow end of write to output active 5 -- -- 5 -- -- ns ? switching waveforms (write cycle) write cycle 1 (1) t wc t wr1 (3) t cw (11) t cw (11) t wp (2) t aw t ohz (4 , 10) t as t wr2 (3) t dh t dw d in d out we ce2 ce1 oe address (5) (5)
bs62 l v 8001 r0201-bs62lv8001 revision 2.4 oct. 2008 7 write cycle 2 (1,6) notes: 1. we must be high during address transitions. 2. the internal write time of the memory is defined by the overlap of ce1 and ce2 active and we low. all signals must be active to initiate a write and any one signal can terminate a write by going inactive. the data input set up and hold timing should be referenced to the second transition edge of the signal that terminates the write. 3. t wr is measured from the earlier of ce1 or we going high or ce2 going low at the end of write cycle. 4. during this period, dq pins are in the out put state so that the input signals of opposite phase to the outputs must not be applied. 5. if the ce1 low transition or the ce2 high tr ansition occurs simultaneously with the we low transitions or after the we transition, output remain in a high impedance state. 6. oe is continuously low (oe = v il ). 7. d out is the same phase of write data of this write cycle. 8. d out is the read data of next address. 9. if ce1 is low and ce2 is high during this per iod, dq pins are in the output state. then the data input signals of opposite phase to the outputs must not be applied to them. 10. transition is measured 500mv from steady state with c l = 5pf. the parameter is guaranteed but not 100% tested. 11. t cw is measured from the later of ce1 going low or ce2 going high to the end of write. t wc t cw (11) t cw (11) t wp (2) t aw t whz (4 , 10) t as t wr2 (3) t dh t dw d in d out we ce2 ce1 address (5) (5) t ow (7) (8) (8 , 9)
bs62 l v 8001 r0201-bs62lv8001 revision 2.4 oct. 2008 8 ? ordering information note: bsi (brilliance semiconductor inc.) assumes no responsibility for the application or use of any product or circuit described he rein. bsi does not authorize its products for use as critical components in any application in which the failure of the bsi product may be exp ected to result in significant injury or death, including life- support systems and critical medical instruments. ? package dimensions package d: dice e: tsop ii-44 f: bga-48-0912 bs62lv8001 x x z y y grade c: +0 o c ~ +70 o c i: -40 o c ~ +85 o c speed 55: 55ns 70: 70ns pkg material g: green, rohs compliant p: pb free, rohs compliant tsop ii-44
bs62 l v 8001 r0201-bs62lv8001 revision 2.4 oct. 2008 9 ? package dimensions (continued) e 0.1 3: symbol "n" is the number of solder balls. 1: controlling dimensio ns are in millimeters. 2: pin#1 dot marking by laser or pad print. n e d notes: 48 12.0 9.0 e1 d1 e 3.75 5.25 0.75 side view d 0.1 d1 1.2 max. e e1 0.25 0.05 solder ball 0.35 0.05 view a 3.375 2.625 48 mini-bga (9mm x 12mm)
bs62 l v 8001 r0201-bs62lv8001 revision 2.4 oct. 2008 10 ? revision history revision no. history draft date remark 2.2 add icc1 characteristic parameter jan. 13, 2006 improve iccsb1 spec. i-grade from 110ua to 50ua at 5.0v 10ua to 8.0ua at 3.0v c-grade from 55ua to 25ua at 5.0v 5.0ua to 4.0ua at 3.0v 2.3 change i-grade operation temperature range may. 25, 2006 - from ?25 o c to ?40 o c change iccdr spec. i-grade from 2.5ua to 4.0ua c-grade from 1.3ua to 2.0ua typical from 0.8 to 0.4ua 2.4 typical value of standby current is replaced by oct. 31, 2008 maximum value in featues and description section remove ?-: normal? (leaded) pkg material in ordering information
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